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tsc87c52 1 matra mhs rev. c 10 sept 1997 preliminary cmos 0 to 33 mhz programmable 8bit microcontroller description temic's tsc87c52 is high performance cmos eprom version of the 80c52 cmos single chip 8 bit microcontroller. the fully static design of the tsc87c52 allows to reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the tsc87c52 retains all the features of the 80c52 with some enhancement: 8 k bytes of internal code memory (eprom); 256 bytes of internal data memory (ram); 32 i/o lines; three 16 bit timers one with countdown and clockout capability; a 6-source, 2-level interrupt structure; a full duplex serial port with framing error detection; a power off flag; and an on-chip oscillator. the tsc87c52 has 2 software-selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the ram, the timers, the serial port and the interrupt system continue to function. in the power down mode the ram is saved and all other functions are inoperative. the tsc87c52 is manufactured using non volatile scmos process which allows it to run up to: 33 mhz with vcc = 5 v 10%. 16 mhz with 2.7 v < vcc < 5.5 v. features 8 kbytes of eprom improved quick pulse programming algorithm secret rom by encryption 256 bytes of ram 64 kbytes program memory space 64 kbytes data memory space 32 programmable i/o lines three 16 bit timer/counters including enhanced timer 2 programmable serial port with framing error detection power control modes twolevel interrupt priority fully static design 0.8 m scmos non volatile process once mode enhanced hooks system for emulation purpose available temperature ranges: commercial industrial available packages: pdip40 (otp) plcc44 (otp) pqfp44 (otp) cqpj44 (uv erasable) cerdip40 (uv erasable)
tsc87c52 2 rev. c 10 sept 1997 preliminary matra mhs block diagram eprom figure 1 tsc87c52 block diagram
tsc87c52 3 matra mhs rev. c 10 sept 1997 preliminary pin configuration p1.0/t2 p1.1/t2ex p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 rst p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss 39 plcc/cqpj 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 14 15 16 17 13 18 19 23 22 21 20 26 25 24 27 28 5 4 3 2 1 6 44 43 42 41 40 p1.4 p1.0/t2 p1.1/t2ex p1.3 p1.2 vss1 vcc p0.0/ad0 p0.2/ad2 p0.3/ad3 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea/vpp reserved p2.7/a15 p2.5/a13 p2.6/a14 p3.6/wr p3.7/rd xtal2 xtal1 vss reserved p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 33 flat pack 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 8 9 10 11 7 12 13 17 16 15 14 20 19 18 21 22 43 42 41 40 39 44 38 37 36 35 34 p1.4 p1.0/t2 p1.1/t2ex p1.3 p1.2 vss1 vcc p0.0/ad0 p0.2/ad2 p0.3/ad3 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea/vpp reserved p2.7/a15 p2.5/a13 p2.6/a14 p1.5 p1.6 p1.7 rst p3.0/rxd reserved p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss reserved p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p1.5 p1.6 p1.7 rst p3.0/rxd reserved p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 vcc p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 ea /vpp ale/prog psen p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 dip figure 2 tsc87c52 pin configuration do not connect reserved pins.
tsc87c52 4 rev. c 10 sept 1997 preliminary matra mhs pin description vss circuit ground potential. vss1 secondary ground (not on dip). provided to reduce ground bounce and improve power supply bypassing. note : this pin is not a substitute for the vss pin. connection is not necessary for proper operation. vcc supply voltage during normal, idle, and power down operation. port 0 port 0 is an 8 bit open drain bi-directional i/o port. port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pullups when emitting 1's. port 0 can sink eight ls ttl inputs. port 0 is used as data bus during eprom programming and program verification. port 1 port 1 is an 8 bit bi-directional i/o port with internal pullups. port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (iil, in the dc parameters section) because of the internal pullups. port 1 can sink/ source three ls ttl inputs. it can drive cmos inputs without external pullups. port1 also serves the functions of the following special features of the tsc87c52 as listed below: port pin alternate function p1.0 p1.1 t2 (external count input to timer/counter 2), clockout t2ex (timer/counter 2 capture/reload trigger and direction control) port 1 receives the loworder address byte during eprom programming and program verification. port 2 port 2 is an 8 bit bi-directional i/o port with internal pullups. port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (iil, in the dc parameters section) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses (movx @dptr). in this application, it uses strong internal pullups when emitting 1's. during accesses to external data memory that use 8 bit addresses (movx @ri), port 2 emits the contents of the p2 special function register. port 2 can sink/source three ls ttl inputs. it can drive cmos inputs without external pullups. some port 2 pins receive the highorder address bits and control signals during eprom programming and program verification. port 3 port 3 is an 8 bit bi-directional i/o port with internal pullups. port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (iil, in the dc parameters section) because of the pullups.
tsc87c52 5 matra mhs rev. c 10 sept 1997 preliminary port 3 also serves the functions of various special features of the temic's c51 family, as listed below: port pin alternate function p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 rxd (serial input port) txd (serial output port) int0 (external interrupt 0) int1 (external interrupt 1) t0 (timer 0 external input) t1 (timer 1 external input) wr (external data memory write strobe) rd (external data memory read strobe) port 3 can sink/source three ls ttl inputs. it can drive cmos inputs without external pullups. some port 3 pins receive control signals during eprom programming and program verification. rst a high level on this pin for two machine cycles while the oscillator is running resets the device. an internal pull-down resistor permits power-on reset using only a capacitor connected to v cc . the port pins will be driven to their reset condition when a minimum vih1 voltage is applied whether the oscillator is started or not (asynchronous reset). ale/prog address latch enable output for latching the low byte of the address during accesses to external memory. ale is activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data memory access at which time one ale pulse is skipped. ale can sink/source 8 ls ttl inputs. it can drive cmos inputs without external pullup. if desired, to reduce emi, ale operation can be disabled by setting bit 0 of sfr location 8eh (mscon). with this bit set, the pin is weakly pulled high. however, ale remains active during movx, movc instructions and external fetches. setting the ale disable bit has no effect if the microcontroller is in external execution mode (ea =0). throughout the remainder of this datasheet, ale will refer to the signal coming out of the ale/prog pin, and the pin will be referred to as the ale/prog pin. psen program store enable output is the read strobe to external program memory. psen is activated twice each machine cycle during fetches from external program memory. (however, when executing out of external program memory, two activations of psen are skipped during each access to external data memory). psen is not activated during fetches from internal program memory. psen can sink/source 8 ls ttl inputs. it can drive cmos inputs without an external pullup. ea /vpp external access enable. ea must be strapped to vss in order to enable the device to fetch code from external program memory locations 0000h to ffffh. note however, that if any of the security bits are programmed, ea will be internally latched on reset. ea should be strapped to vcc for internal program execution. this pin also receives the programming supply voltage (vpp) during eprom programming. xtal1 input to the inverting amplifier that forms the oscillator. receives the external oscillator signal when an external oscillator is used. xtal2 output from the inverting amplifier that forms the oscillator. this pin should be floated when an external oscillator is used.
tsc87c52 6 rev. c 10 sept 1997 preliminary matra mhs new and enhanced features in comparison to the original 80c52, the tsc87c52 implements some new and enhanced features. the new features are the power off flag, the once mode and the ale disabling. the enhanced features are located in the uart and the timer 2. power off flag the power off flag allows the user to distinguish between a `cold start' reset and a `warm start' reset. a cold start reset is one that is coincident with vcc being turned on to the device after it was turned off. a warm start reset occurs while vcc is still applied to the device and could be generated for example by an exit from power down. the power off flag (pof) is located in pcon at bit location 4 (see table 1). pof is set by hardware when vcc rises from 0 to its nominal voltage. the pof can be set or cleared by software allowing the user to determine the type of reset. table 1 pcon power control register (87h) 76543210 smod1 smod0 pof gf1 gf0 pd idl symbol description smod1 serial port mode bit 1 , new name of smod bit set to select double baud rate in mode 1,2 or 3. smod0 serial port mode bit 0 set to to select fe bit in scon. clear to select sm0 bit in scon. reserved do not write 1 in this bit. pof power off flag set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software. clear by software to recognize next reset type. gf1 general purpose flag set by software for general purpose usage. clear by software for general purpose usage. gf0 general purpose flag set by software for general purpose usage. clear by software for general purpose usage. pd power down mode bit set to enter power down mode. clear by hardware when reset occurs. idl idle mode bit set to enter idle mode. clear by hardware when interrupt or reset occur. the reset value of pcon is 00xx 0000b. once mode the once mode facilitates testing and debugging of systems using tsc87c52 without the tsc87c52 having to be removed from the circuit. the once mode is invoked by driving certain pins of the tsc87c52, the following sequence must be exercised. pull ale low while the device is in reset (rst high) and psen is high. hold ale low as rst is deactivated.
tsc87c52 7 matra mhs rev. c 10 sept 1997 preliminary while the tsc87c52 is in once mode, an emulator or test cpu can be used to drive the circuit. table 2 shows the status of the port pins during once mode. normal operation is restored when normal reset is applied. table 2 external pin status during once mode ale psen port 0 port 1 port 2 port 3 xtal1/2 weak pullup weak pullup float weak pullup weak pullup weak pullup active ale disabling the ale signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. nevertheless, during internal code execution, ale signal is still generated. in order to reduce emi, ale signal should be disabled by setting ao bit. the ao bit is located in mscon at bit location 0 (see table 3). as soon as ao is set, ale is no longer output but remains active during movx and movc instructions and external fetches. during ale disabling, ale pin is weakly pulled high. table 3 mscon miscellaneous control register (8eh) 76543210 ao symbol description reserved do not write 1 in these bits. ao ale output bit set to disable ale operation during internal fetches. clear to restore ale operation during internal fetches. the reset value of mscon is xxxx xxx0b. uart the uart in the tsc87c52 operates identically to the uart in the 80c51 but includes the following enhancement. for a complete understanding of the tsc87c52 uart please refer to the description in the 80c51 hardware description guide. framing error detection framing error detection allows the serial port to check for missing stop bits in the communication in mode 1, 2 or 3. a missing stop bit can be caused for example by noise on the serial lines or transmission by two cpus simultaneously. if a stop bit is missing a framing error bit (fe) is set. the fe bit can be checked in software after each reception to detect communication errors. once set, the fe bit must be cleared in software. a valid stop bit will not clear fe. the fe bit is located in scon at bit location 7. it shares the same bit location as sm0 (see table 4). the new control bit smod0 in pcon (see table 1) determines whether the sm0 or fe bit is accessed (see figure 3), so whether the framing error detection is enabled or not. if smod0 is set then scon.7 functions as fe, if smod0 is cleared then scon.7 functions as sm0. once set, the fe bit must be cleared by software. a valid stop bit will not clear fe. when uart is in mode 1 (8bit mode), ri flag is set during stop bit whether or not framing error is enabled (see figure 4).
tsc87c52 8 rev. c 10 sept 1997 preliminary matra mhs when in mode 2 and 3 (9bit mode), ri flag is set during stop bit if framing error is enabled or during ninth bit if not (see figure 5). ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof smod0 smod1 to uart framing error control sm0 to uart mode control set fe bit if stop bit is 0 (framing error) figure 3 framing error block diagram data byte ri smod0=x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1 figure 4 enhanced uart timing diagram in mode 1 ri smod0=0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0=1 fe smod0=1 figure 5 enhanced uart timing diagram in mode 2 and 3 table 4 scon serial control register (98h) 76543210 sm0/fe sm1 sm2 ren tb8 rb8 ti ri symbol description fe sm0 framing error bit (smod0 bit set) set by hardware when an invalid stop bit is detected. clear to reset the error state, not cleared by a valid stop bit. serial mode bit 0 (smod0 bit cleared) used with sm1 to select serial mode. sm1 serial mode bit 1 used with sm0 to select serial mode. sm2 multiprocessor communication enable bit set to enable multiprocessor communication feature in mode 2 and 3. clear to disable multiprocessor communication feature.
tsc87c52 9 matra mhs rev. c 10 sept 1997 preliminary description symbol ren serial reception enable bit set to enable serial reception. clear to disable serial reception. tb8 ninth bit to transmit in mode 2 and 3 set to transmit a logic 1 in the 9th bit. clear to transmit a logic 0 in the 9th bit. rb8 ninth bit received in mode 2 and 3 set by hardware if 9th bit received is logic 1. clear by hardware if 9th bit received is logic 0. ti transmit interrupt flag set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. clear to acknowledge interrupt. ri receive interrupt flag set by hardware at the end of the 8th bit time in mode 0, see figure 4 and figure 5 in the other modes. clear to acknowledge interrupt. the reset value of scon is 0000 0000b. timer 2 the timer 2 in the tsc87c52 operates identically to the timer 2 in the 80c52 but includes the following enhancements. for a complete understanding of the tsc87c52 timer 2 please refer to the description in the 80c51 hardware description guide. autoreload (up or down counter) enhanced timer 2 can now be programmed to count up or down when configured in its 16bit autoreload mode. this feature is controlled by the dcen (down counter enable) bit. dcen is located in t2mod at bit location 0 (see table 5). setting the dcen bit enables timer 2 to count up or down as shown in figure 6. in this mode the t2ex pin controls the direction of count. a logic 1 at t2ex makes timer 2 count up. the timer will overflow at ffffh and set the tf2 bit. this overflow also causes the 16bit value in rcap2h and rcap2l to be reloaded into the timer registers, th2 and tl2, respectively. a logic 0 at t2ex makes timer 2 count down. now the timer underflows when th2 and tl2 equal the values stored in rcap2h and rcap2l. the underflow sets the tf2 bit and causes ffffh to be reloaded into the timer registers. the exf2 bit toggles whenever timer 2 overflows or underflows. in this operating mode, exf2 does not flag an interrupt. count direction 1= up 0= down (down counting reload value) c/t2 tf2 tr2 12 osc t2 t2ex exf2 th2 (8bit) tl2 (8bit) rcap2h (8bit) rcap2l (8bit) ffh (8bit) ffh (8bit) toggle (up counting reload value) timer 2 interrupt figure 6 timer 2 autoreload mode up/down counter
tsc87c52 10 rev. c 10 sept 1997 preliminary matra mhs programmable clock output a 50% duty cycle clock can be programmed to come out on p1.0. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed to input external clock for timer/counter 2 or to output a 50% duty cycle clock from frequency fosc/2 18 to frequency fosc/4 (61 hz to 4 mhz at a 16 mhz operating frequency). the clockout frequency depends on the oscillator frequency and the reload value of timer 2 capture registers rcap2h and rcap2l as shown in this equation: oscillator frequency clockout frequency= 4 ? (65536 rcap2h,rcap2l) to configure the timer/counter 2 as a clock generator, bit c/t2 in t2con (bit location 1) must be cleared and bit t2oe must be set. bit tr2 in t2con starts and stops the timer (see figure 7). t2oe is located in t2mod at bit location 1 (see table 5). in the clockout mode, timer 2 rollovers will not generate an interrupt. this is similar to when timer 2 is used as a baudrate generator. it is possible to use timer 2 as a baudrate generator and as clock generator simultaneously. note however, that the baudrate and clockout frequencies can not be determined independently from one another since they both use rcap2h and rcap2l. tr2 2 osc overflow t2ex exf2 th2 (8bit) tl2 (8bit) timer 2 interrupt exen2 rcap2h (8bit) rcap2l (8bit) t2oe c/t2 t2 2 figure 7 timer 2 clockout mode table 5 t2mod timer 2 control register (c9h) 76543210 t2oe dcen symbol description reserved do not write 1 in these bits. t2oe timer 2 output enable bit set to program p1.0/t2 as clock output. clear to program p1.0/t2 as clock input or i/o port. dcen decrement enable bit set to enable timer 2 as up/down counter. clear to disable timer 2 as up/down counter. the reset value of t2mod is xxxx xx00b.
tsc87c52 11 matra mhs rev. c 10 sept 1997 preliminary eprom eprom structure the tsc87c52 eprom is divided in two different arrays: the code array: 8 kbytes. the encryption array: 64 bytes. in addition a third non programmable array is implemented: the signature array: 4 bytes. eprom lock system the program lock system, when programmed, protects the onchip program against software piracy. encryption array within the eprom array are 64 bytes of encryption array that are initially unprogrammed (all 1's). every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. this byte is then exclusivenor'ed (xnor) with the code byte, creating an encryption verify byte. the algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. when using the encryption array, one important factor needs to be considered. if a byte has the value ffh, verifying the byte will produce the encryption byte value. if a large block (>64 bytes) of code left unprogrammed, a verification routine will display the content of the encryption array. for this reason all the unused code bytes should be programmed with random values. this will ensure program protection. eprom programming setup modes in order to program and verify the eprom or to read the signature bytes, the tsc87c52 is placed in specific setup modes (see figure 8). control and program signals must be held at the levels indicated in table 6. definition of terms address lines: p1.0p1.7, p2.0p2.4 respectively for a0a12 data lines: p0.0p0.7 for d0d7 control signals: rst, psen , p2.6, p2.7, p3.3, p3.6, p3.7. program signals: ale/prog , ea /vpp. table 6 eprom setup modes mode rst psen ale/ prog ea /vpp p2.6 p2.7 p3.3 p3.6 p3.7 program code data 1 0 12.75v 0 1 1 1 1 verify code data 1 0 1 1 0 0 1 1 program encryption array address 03fh 1 0 12.75v 0 1 1 0 1 read signature bytes 1 0 1 1 0 0 0 0
tsc87c52 12 rev. c 10 sept 1997 preliminary matra mhs +5v vcc p0.0p0.7 p1.0p1.7 p2.0p2.4 vss gnd d0d7 a0a7 a8a12 rst ea /vpp ale/prog psen p2.6 p2.7 p3.3 p3.7 p3.6 xtal1 4 to 6 mhz control signals* program signals* * see table 6 for proper value on these inputs figure 8 setup modes configuration programming algorithm the improved quick pulse algorithm is based on the quick pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 5. to program the tsc87c52 the following sequence must be exercised: step 1: input the valid address on the address lines. step 2: input the appropriate data on the data lines. step 3: activate the combination of control signals. step 4: raise ea /vpp from vcc to vpp (typical 12.75v). step 5: pulse ale/prog 5 times. repeat step 1 through 5 changing the address and data for the entire array or until the end of the object file is reached (see figure 9). verify algorithm code array verify must be done after each byte or block of bytes is programmed. in either case, a complete verify of the programmed array will ensure reliable programming of the tsc87c52. to verify the tsc87c52 code the following sequence must be exercised : step 1: activate the combination of program signals. step 2: input the valid address on the address lines. step 3: input the appropriate data on the data lines. step 4: activate the combination of control signals. repeat step 2 through 4 changing the address and data for the entire array (see figure 9). the encryption array cannot be directly verified. verification of the encryption array is done by observing that the code array is well encrypted.
tsc87c52 13 matra mhs rev. c 10 sept 1997 preliminary control signals data in ale/prog a0a12 programming cycle 1 2 3 5 4 10us 100us d0d7 ea /vpp data out read/verify cycle 12.75v 5v 0v figure 9 programming and verification signal's waveform signature bytes the tsc87c52 has four signature bytes in location 30h, 31h, 60h and 61h. to read these bytes follow the procedure for eprom verify but activate the control lines provided in table 6 for read signature bytes. table 7 shows the content of the signature byte for the tsc87c52 . table 7 signature bytes content location contents comment 30h 58h customer selection byte: temic 31h 58h family selection byte: c51 60h adh tsc87c52 61h xxh product revision number eprom erasure (windowed packages only) erasing the eprom erases the code array and also the encryption array returning the parts to full functionality. erasure leaves all the eprom cells in a 1's state. erasure characteristics the recommended erasure procedure is exposure to ultraviolet light (at 2537 ?) to an integrated dose at least 15 wsec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. erasure of the eprom begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 ?. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window.
tsc87c52 14 rev. c 10 sept 1997 preliminary matra mhs electrical characteristics absolute maximum ratings (1) ambiant temperature under bias: c = commercial 0 c to 70 c . . . . . . . . . . . . . . . . . . . . i = industrial 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . storage temperature 65 c to + 150 c . . . . . . . . . . . voltage on vcc to vss 0.5 v to + 7 v . . . . . . . . . . . . voltage on vpp to vss 0.5 v to + 13 v . . . . . . . . . . . voltage on any pin to vss 0.5 v to vcc + 0.5 v . . . power dissipation 1 w (2) . . . . . . . . . . . . . . . . . . . . . . . notice: 1. s tresses at or above those listed under a absolute maximum rat- ingso may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. 2. this value is based on the maximum allowable die temperature and the thermal resistance of the package .
tsc87c52 15 matra mhs rev. c 10 sept 1997 preliminary dc parameters for standard voltage, commercial and industrial temperature range t a = 0 c to +70 c; vss = 0v; vcc = 5v 10%; f = 0 to 33 mhz. t a = 40 c to +85 c; vss = 0v; vcc = 5v 10%; f = 0 to 33 mhz. symbol parameter min typ max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage except xtal1, rst 0.2 vcc + 0.9 vcc + 0.5 v vih1 input high voltage, xtal1, rst 0.7 vcc vcc + 0.5 v vol output low voltage, ports 1, 2, 3 (6) 0.3 0.45 1.0 v v v iol = 100 m a (4) iol = 1.6ma (4) iol = 3.5ma (4) vol1 output low voltage, port 0, ale, psen (6) 0.3 0.45 1.0 v v v iol = 200 m a (4) iol = 3.2ma (4) iol = 7.0ma (4) voh output high voltage, ports 1, 2, 3 vcc 0.3 vcc 0.7 vcc 1.5 v v v ioh = 10 m a ioh = 30 m a ioh = 60 m a vcc = 5v 10% voh1 output high voltage, port 0, ale, psen vcc 0.3 vcc 0.7 vcc 1.5 v v v ioh = 200 m a ioh = 3.2ma ioh = 7.0ma vcc = 5v 10% rrst rst pulldown resistor 50 90 (5) 200 k w iil logical 0 input current ports 1, 2 and 3 50 m a vin = 0.45v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current, ports 1, 2, 3 650 m a vin = 2.0v cio capacitance of i/o buffer 10 pf fc = 1mhz, t a = 25 c ipd power down current 10 (5) 50 m a vcc = 2.0v to 5.5v (3) icc power supply current (7) freq = 1 mhz icc op icc idle freq = 6 mhz icc op icc idle freq 12 mhz icc op = 1.25 frecq (mhz) + 5 ma icc idle = 0.36 freq (mhz) + 2.7 ma (5) 13@12mhz 16@16mhz 5.5@12mhz 7@16mhz 1.8 1 10 4 ma ma ma ma ma ma vcc = 5.5v (1) vcc = 5.5v (2)
tsc87c52 16 rev. c 10 sept 1997 preliminary matra mhs dc parameters for low voltage, commercial and industrial temperature range t a = 0 c to +70 c; vss = 0v; vcc = 2.7v to 5v 10%; f = 0 to 16 mhz. t a = 40 c to +85 c; vss = 0v; vcc = 2.7v to 5v 10%; f = 0 to 16 mhz. symbol parameter min typ max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage except xtal1, rst 0.2 vcc + 0.9 vcc + 0.5 v vih1 input high voltage, xtal1, rst 0.7 vcc vcc + 0.5 v vol output low voltage, ports 1, 2, 3 (6) 0.45 v iol = 0.8ma (4) vol1 output low voltage, port 0, ale, psen (6) 0.45 v iol = 1.6ma (4) voh output high voltage, ports 1, 2, 3 0.9 vcc v ioh = 10 m a voh1 output high voltage, port 0, ale, psen 0.9 vcc v ioh = 40 m a iil logical 0 input current ports 1, 2 and 3 50 m a vin = 0.45v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current, ports 1, 2, 3 650 m a vin = 2.0v rrst rst pulldown resistor 50 90 (5) 200 k w cio capacitance of i/o buffer 10 pf fc = 1mhz, t a = 25 c ipd power down current tbd (5) tbd m a vcc = 2.0v to 5.5v (3) icc power supply current (7) active mode 16mhz idle mode 16mhz tbd (5) tbd (5) tbd tbd ma ma vcc = 3.3v (1) vcc = 3.3v (2) notes for dc electrical characteristics 1. operating icc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl = 5 ns (see figure 13), vil = vss + 0.5v, vih = vcc 0.5v; xtal2 n.c.; ea = rst = port 0 = vcc. icc would be slightly higher if a crystal oscillator used (see no tag). 2. idle icc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl = 5ns, vil = vss + 0.5v, vih = vcc0.5 v; xtal2 n.c; port 0 = vcc; ea = rst = vss (see figure 11). 3. power down icc is measured with all output pins disconnected; ea = vss, port 0 = vcc; xtal2 nc.; rst = vss (see no tag). 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the vols of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus oper ation. in the worst cases (capacitive loading 100pf), the noise pulse on the ale line may exceed 0.45v with maxi vol peak 0.6v. a schmitt trigger u se is not neces- sary. 5. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and 5v. 6. under steady state (nontransient) conditions, iol must be externally limited as follows: maximum iol per port pin: 10 ma maximum iol per 8bit port: port 0: 26 ma ports 1, 2 and 3: 15 ma maximum total iol for all output pins: 71 ma if iol exceeds the test condition, vol may exceed the related specification. pins are not guaranteed to sink current greater th an the listed test condi- tions. 7. for other values, please contact your sales office.
tsc87c52 17 matra mhs rev. c 10 sept 1997 preliminary vcc vcc icc (nc) clock signal vcc all other pins are disconnected. rst xtal2 xtal1 vss vcc p0 ea figure 10 icc test condition, active mode rst ea xtal2 xtal1 vss vcc vcc icc (nc) p0 vcc all other pins are disconnected. clock signal figure 11 icc test condition, idle mode rst ea xtal2 xtal1 vss vcc vcc icc (nc) p0 vcc all other pins are disconnected. figure 12 icc test condition, power down mode vcc0.5v 0.45v 0.7vcc 0.2vcc0.1 tclch tchcl tclch = tchcl = 5ns. figure 13 clock signal waveform for icc tests in active and idle modes
tsc87c52 18 rev. c 10 sept 1997 preliminary matra mhs ac parameters explanation of the ac symbols each timing symbol has 5 characters. the first character is always a ato (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. example: tavll = time for address valid to ale low. tllpl = time for ale low to psen low. t a = 0 to +70 c; vss = 0v vcc = 5v 10%; 0 to 12mhz t a = 40 c to +85 c; vss = 0v; vcc = 5v 10%; f = 0 to 12mhz. (load capacitance for port 0, ale and psen = 100pf; load capacitance for all other outputs = 80 pf.) external program memory characteristics symbol parameter 0 to 12mhz un i ts symbol parameter min max units tlhll ale pulse width 2tclcl 40 ns tavll address valid to ale tclcl 40 ns tllax address hold after ale tclcl 30 ns tlliv ale to valid instruction in 4tclcl 100 ns tllpl ale to psen tclcl 30 ns tplph psen pulse width 3tclcl 45 ns tpliv psen to valid instruction in 3tclcl 105 ns tpxix input instruction hold after psen 0 ns tpxiz input instruction floatafter psen tclcl 25 ns tpxav psen to address valid tclcl 8 ns taviv address to valid instruction in 5tclcl 105 ns tpxav psen low to address float 10 ns external program memory read cycle tpliv tplaz ale psen port 0 port 2 a0a7 a0a7 instr in instr in instr in address or sfrp2 address a8a15 address a8a15 12 tclcl taviv tlhll tavll tlliv tllpl tplph tpxav tpxix tpxiz tllax
tsc87c52 19 matra mhs rev. c 10 sept 1997 preliminary external data memory characteristics symbol parameter 0 to 12mhz un i ts symbol parameter min max units trlrh rd pulse width 6tclcl100 ns twlwh wr pulse width 6tclcl100 ns trldv rd to valid data in 5tclcl165 ns trhdx data hold after rd 0 ns trhdz data float after rd 2tclcl60 ns tlldv ale to valid data in 8tclcl150 ns tavdv address to valid data in 9tclcl165 ns tllwl ale to wr or rd 3tclcl50 3tclcl+50 ns tavwl address to wr or rd 4tclcl130 ns tqvwx data valid to wr transition tclcl50 ns tqvwh data setup to wr high 7tclcl150 ns twhqx data hold after wr tclcl50 ns trlaz rd low to address float 0 ns twhlh rd or wr high to ale high tclcl40 tclcl+40 ns external data memory write cycle tqvwh tllax ale psen wr port 0 port 2 a0a7 data out address or sfrp2 tavwl tllwl tqvwx address a8a15 or sfr p2 twhqx twhlh twlwh
tsc87c52 20 rev. c 10 sept 1997 preliminary matra mhs external data memory read cycle ale psen rd port 0 port 2 a0a7 data in address or sfrp2 tavwl tllwl trlaz address a8a15 or sfr p2 trhdz twhlh trlrh tlldv trhdx tavdv tllax serial port timing shift register mode symbol parameter 0 to 12mhz un i ts symbol parameter min max units txlxl serial port clock cycle time 12tclcl ns tqvhx output data setup to clock rising edge 10tclcl133 ns txhqx output data hold after clock rising edge 2tclcl117 ns txhdx input data hold after clock rising edge 0 ns txhdv clock rising edge to input data valid 10tclcl133 ns shift register timing waveforms valid valid input data valid valid 0123456 8 7 ale clock output data write to sbuf clear ri txlxl tqvxh txhqx txhdv txhdx set ti set ri instruction 01234567 valid valid valid valid
tsc87c52 21 matra mhs rev. c 10 sept 1997 preliminary eprom programming and verification characteristics t a = 21 c to 27 c; vss = 0v; vcc = 5v 10%. symbol parameter min max units vpp programming supply voltage 12.5 13 v ipp programming supply current 75 ma 1/tclcl oscillator frquency 4 6 mhz tavgl address setup to prog low 48 tclcl tghax adress hold after prog 48 tclcl tdvgl data setup to prog low 48 tclcl tghdx data hold after prog 48 tclcl tehsh (enable) high to vpp 48 tclcl tshgl vpp setup to prog low 10 m s tghsl vpp hold after prog 10 m s tglgh prog width 90 110 m s tavqv address to valid data 48 tclcl telqv enable low to data valid 48 tclcl tehqz data float after enable 0 48 tclcl tghgl prog high to prog low 10 m s eprom programming and verification waveforms tghgl tghsl tehsh ale/prog tavgl 5 pulses tdvgl p0 p1.0p1.7 p2.0p2.4 ea/vcc control signals (enable) address data in vcc vpp vcc tghax tghdx tglgh tshgl address data out tavqv telqv tehqz programming verification
tsc87c52 22 rev. c 10 sept 1997 preliminary matra mhs external clock drive characteristics (xtal1) symbol parameter min max units tclcl oscillator period 30 ns tchcx high time 5 ns tclcx low time 5 ns tclch rise time 5 ns tchcl fall time 5 ns external clock drive waveforms vcc0.5v 0.45v 0.7vcc 0.2vcc0.1 tchcl tclcx tclcl tclch tchcx ac testing input/output waveforms input/output 0.2 vcc + 0.9 0.2 vcc 0.1 vcc 0.5 v 0.45 v ac inputs during testing are driven at vcc 0.5 for a logic a1o and 0.45v for a logic a0o. timing measurement are made at vih min for a logic a1o and vil max for a logic a0o. float waveforms float voh 0.1 v vol + 0.1 v vload vload + 0.1 v vload 0.1 v for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded voh/vol level occurs. iol/ioh 20ma.
tsc87c52 23 matra mhs rev. c 10 sept 1997 preliminary clock waveforms data pcl out data pcl out data pcl out sampled sampled sampled state4 state5 state6 state1 state2 state3 state4 state5 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 float float float these signals are not activated during the execution of a movx instruction indicates address transitions external program memory fetch float data sampled dpl or rt out indicates dph or p2 sfr to pch transition pcl out (if program memory is external) pcl out (even if program memory is internal) pcl out (if program memory is external) old data new data p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled rxd sampled internal clock xtal2 ale psen p0 p2 (ext) read cycle write cycle rd p0 p2 wr port operation mov port src mov dest p0 mov dest port (p1. p2. p3) (includes into. int1. to t1) serial port shift clock txd (mode 0) data out dpl or rt out indicates dph or p2 sfr to pch transition p0 p2 rxd sampled this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125ns. this propagation delay is dependent on variables such as temperature and pin loading. propagation also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50ns. the other signals are typically 85ns. propagation delays are incorporated in the ac specifications.
tsc87c52 24 rev. c 10 sept 1997 preliminary matra mhs ordering information tsc 87c52 20 12: 12 mhz version 16: 16 mhz version 20: 20 mhz version 25: 25 mhz version 33: 33 mhz version l16: low power (vcc: 2.75.5v, freq.: 016 mhz) part number 87c52: programmable rom temic semiconductor microcontroller product line c temperature range c: commercial 0 to 70 c i: industrial 40 to 85 c otp packaging a: pdil 40 b: plcc 44 c: pqfp 44 (f1) d: pqfp 44 (f2) e: vqfp 44 (1.4mm) f: tqfp 44 (1mm) g: cdil 40 (.6) h: lcc 44 i: cqpj 44 epromuv erasable j: window cdil 40 k: window cqpj 44 b conditioning r: tape & reel d: dry pack b: tape & reel and dry pack r

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